Semiconductor memory devices are widely used in many consumer, commercial and other devices. Semiconductor memory devices may be characterized as volatile memory devices or nonvolatile memory devices. In the volatile memory devices, information may be stored by setting up a logic state of bistable flip-flop such as in a static random access memory, through charging of a capacitor as in a dynamic random access memory and/or using other techniques. The data are stored and can be read out as long as the power is applied, and is lost when the power is turned off.
Nonvolatile memory devices such as MROM, PROM, EPROM, and EEPROM are capable of storing the data, even with the power turned off. The nonvolatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. A combination of single-chip volatile as well as memory storage modes is also available in devices such as SRAM (nvRAM). In addition, many special memory architectures have evolved which contain some additional logic circuitry to match their performance for application-specific tasks.
In nonvolatile semiconductor memory devices, MROM, PROM, and EPROM are generally not erasable and readable freely, so that it is generally difficult for users to reprogram the memory. Unlike this, EEPROM devices are electrically erasable and writable. Flash EEPROM (hereinafter, referred to as a “flash memory) may provide a higher density as compared with a conventional EEPROM. Moreover, a NAND-type flash memory may provide higher density than a NOR-type flash memory. The various classifications and architectures for various types of nonvolatile memory devices are well known to those having skill in the art and need not be described further herein.
FIG. 1 is a block diagram of a conventional NAND-type flash memory device. Referring to FIG. 1, a NAND-type flash memory device 10 includes a memory cell array 20, a row selection circuit 40 that is denoted by “X-SEL” in FIG. 1, and a page buffer circuit 60. A memory cell array 20 includes a plurality of cell strings (or NAND strings) 21, which are connected to bit lines BL0-BLm, respectively. A cell string 21 of a respective column is formed of a string selection transistor (SST) as a first selection transistor, a ground selection transistor (GST) as a second selection transistor, and a plurality of flash EEPROM cells or other nonvolatile memory cells (MC0-MCn) that are serially connected between the selection transistors SST and GST. The string selection transistor (SST) of a respective column has a drain and a gate. The drain is connected to a corresponding bit line, and the gate is connected to a string selection line (SSL). The ground selection transistor (GST) has a source connected to a common source line (CSL) and a gate connected to a ground selection line (GSL). Memory cells (MCn-MC0) are serially connected between the source of the string selection transistor (SST) and the drain of the ground selection transistor (GST). Cells of the respective cell strings may be formed of floating gate transistors, and control gates of these transistors are connected to corresponding word lines (WLn-WL0).
The string selection line (SSL), word lines (WL0-WLn), and ground selection line (GSL) are electrically connected to the row selection circuit 40. The row selection circuit 40 selects one of the word lines according to row address information and provides word line voltages according to the respective operation modes to the selected word line and non-selected word lines. For example, the row selection circuit 40 provides a program voltage to a word line that is selected during a program operation mode and a pass voltage to non-selected word lines. The row selection circuit 40 provides a ground voltage GND to a word line selected during a reading operation mode and a read voltage to non-selected word lines. The program voltage, the pass voltage, and the read voltage are generally higher voltage than a power supply voltage. The bit lines BL0-BLm are electrically connected to the page buffer circuit 60. The page buffer circuit 60 senses data from memory cells of a selected word line through the bit lines BL0-BLm in read/verification operation mode. In addition, the page buffer circuit 60 respectively provides a power voltage (or a program-inhibit voltage) or a ground voltage (or a program voltage) to the bit lines BL0-BLm according to data to be programmed in a program operation mode. Page buffers respectively corresponding to the bit lines BL0-BLm may be provided in the page buffer circuit 60. Each page buffer can be embodied so as to share two bit lines. The operation of a nonvolatile device 10 as illustrated in FIG. 1 is well known to those having skill in the art and need not be described further herein.
In the NAND-type flash memory device, as is well known, a cell not to be programmed from the viewpoint of a cell structure may be undesirably soft-programmed. This is often called a “program disturbance”. The program disturbance of the program inhibited cell can be prevented by enhancing a channel voltage of a cell string including the program inhibited cell. This is often called a “self-boosting scheme”. The channel voltage depends on a pass voltage that is respectively supplied to non-selected word lines. The pass voltage becomes high, which can alleviate a degree of soft programming of the program inhibited cell. On the other hand, if the pass voltage becomes high, memory cells connected to each of non-selected word lines may be soft programmed by the pass voltage. This is often called a “pass disturbance”. Accordingly, the pass voltage level may be determined by considering the above-mentioned conditions.
The above-mentioned program inhibition method utilizing a self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Methods Of Programming Flash EEPROM Integrated Circuit Memory Devices To Prevent Inadvertent Programming Of Non designated NAND Memory Cells Therein” and U.S. Pat. No. 5,991,202 entitled “Method For Reducing Program Disturb During Self-Boosting In A NAND Flash Memory”, both of whose disclosures are incorporated herein by reference.
In the NAND-type flash memory device, multiple memory cells connected to one word line may be programmed at the same time. In addition, the memory cells may be programmed several times, and this is generally called a “partial program scheme”. For instance, as shown in FIG. 2, it is assumed that only data to be programmed in a memory region of the bit lines BL0-BLi is loaded in the page buffer circuit 60 (see oblique lines in FIG. 2). Since the memory cells of a region where data is loaded, the memory cells of a memory region where data is not loaded and bit lines BLi+1−BLm are connected to the same word line, a program voltage is supplied to the memory cells of the same word line irrespective of a data loading position. A program operation is performed, and then a program verification operation is performed, as is well known.
In accordance with the program verification operation, the page buffer circuit 60 senses and latches data from the memory cells of a selected row (or page). The program state of the sensed data may be detected by a wired-OR mode in a column scan mode. In accordance with a column scan mode, sensed data values are selected through a column selection circuit (not shown) by a predetermined unit (e.g., x8, x16, and so forth), and then whether or not the selected data values indicate a program state is detected. If the selected data values indicate a program state, the data values by a next predetermined unit are selected. This program verification operation is performed with respect to all memory cells. That is, the program verification operation employing a column scan mode is performed with respect to all memory cells of the selected page irrespective of the amount of data to be programmed. For instance, referring to FIG. 2, even though memory cells connected to bit lines BL0-BLi are programmed substantially, the program verification operation is performed with respect to the memory cells connected to bit lines BL0-BLi. This means that the above-mentioned program verification operation utilizing the column scan mode may be inefficient.
Published U.S. Patent Application 2004/0027901 A1, published Feb. 12, 2004, describes a nonvolatile semiconductor memory device. As stated in the Abstract of this published U.S. Patent Application, a nonvolatile semiconductor memory device capable of performing page programming at high speeds is provided. This nonvolatile memory device includes a cell array with a matrix of rows and columns of electrically writable and erasable nonvolatile memory cells, and a write control circuit which writes or “programs” one-page data into this cell array at a plurality of addresses within one page. The write control circuit is operable to iteratively perform iteration of a write operation for the plurality of addresses corresponding to one page and iteration of a verify-read operation of the plurality of addresses after writing until verify-read check is passed with respect to every address involved. Regarding an address or addresses with no cells to be written any more, the write control circuit skips the write operation and the after-write verify-read operation.